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CHANGE LOG for 7 Series FPGAs Transceivers Wizard V2.5

Release Date:  April 3, 2013 
--------------------------------------------------------------------------------


Table of Contents

1. INTRODUCTION 
2. DEVICE SUPPORT    
3. NEW FEATURE HISTORY   
4. RESOLVED ISSUES 
5. KNOWN ISSUES & LIMITATIONS 
6. TECHNICAL SUPPORT & FEEDBACK
7. CORE RELEASE HISTORY 
8. LEGAL DISCLAIMER 

--------------------------------------------------------------------------------

1. INTRODUCTION

  This file contains the change log for all released versions of the Xilinx 
  LogiCORE IP core 7 Series FPGAs Transceivers Wizard. 
  
  For the latest core updates, see the product page at:

    <A HREF="http://www.xilinx.com/products/intellectual-property/7-Series_FPGA_Transceivers_Wizard.htm">www.xilinx.com/products/intellectual-property/7-Series_FPGA_Transceivers_Wizard.htm</A>

  For installation instructions for this release, please go to:

    <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm">www.xilinx.com/ipcenter/coregen/ip_update_install_instructions.htm</A>

  For system requirements, see:

    <A HREF="http://www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm">www.xilinx.com/ipcenter/coregen/ip_update_system_requirements.htm</A>


2. DEVICE SUPPORT 

  2.1. ISE

    The following device families are supported by the core for this release:

    All 7 Series devices  


3. NEW FEATURE HISTORY

  3.1 ISE

    v2.5  

    - Support for Production Silicon for GTH and GTP. 

    - New Protocol Templates added for GTH - SRIO multi lane, JESD204

    - New Protocol Templates added for GTP - JESD204 


    v2.4  

    - Support for General ES and Production Silicon for GTX

    - Support for General ES for GTH 

    - Support for Initial ES for GTP 

    - Support for Initial ES for GTZ

    - New Protocol Templates added for GTX - CAUI, 10GBASE-KR 

    - New Protocol Templates added for GTH - XLAUI, 10GBASE-R 
   


    v2.3  

    - Support for General ES and Production Silicon for GTX

    - Support for General ES for GTH 

    - Support for Initial ES for GTP 

    - Support for Initial ES for GTZ

    - New Protocol Templates added for GTX -  

    - New Protocol Templates added for GTH - Display Port, OC192 
   
    - New Protocol Templates added for GTP - CEI-6, Aurora 8B10B, Aurora64B66B 

    - New Protocol Templates added for GTZ - Aurora 64B66B 



    v2.2  

    - Support for GTZ Transceiver

    - Support for General ES and Production Silicon for GTX

    - Support for Initial ES for GTH 

    - Support for PCIE Gen1/Gen2 protocol for GTP Transceiver 
 
    - Enhanced Example Design for GTP

    - New Protocol Templates added for GTX - JESD204 

    - New Protocol Templates added for GTH - Aurora 8B/10B 
   
    - New Protocol Templates added for GTP - SRIO Gen1/Gen2



    v1.5

    - Support for Initial ES for GTX


4. RESOLVED ISSUES 


  4.1 ISE

    The following issues are resolved in the indicated IP versions:

    v2.5
      - Added synchronisers for all CDC signals.

      - Updated GUI to be complaint with DS181, DS182 and DS183

      - Updated PCIE Wrapper for GTH and GTP Production Si.


5. KNOWN ISSUES & LIMITATIONS 

  - For GTH and GTP, the Wizard generates settings compatible for Prodcution Si. HW validation
    is of these settings is work in progress.

  - The Wizard generates Verilog wrappers for GTZ. VHDL is not supported.

  - For GTZ designs, the Wizard supports line rates and reference clocks shown in the GUI.
    No other values are tested or validated in hardware.

  - It is recommended that the Beachfront module generated for GTZ designs should NOT be
    modified by the user. Any edits made by the user might lead to unexpected results.

  - Please note that Vivado flow should be used for implementation of all SSIT devices

  - Please note that the protocol templates provided by the Wizard are not characterised on
    hardware

  - Please refer AR 43244 - <A HREF="http://www.xilinx.com/support/answers/43244.htm">www.xilinx.com/support/answers/43244.htm</A> for information
    on GTX Initial ES Settings

  - Please refer AR 47128 - <A HREF="http://www.xilinx.com/support/answers/47128.htm">www.xilinx.com/support/answers/47128.htm</A> for information 
    on GTH Initial ES Settings

  - Please refer AR 45360 - <A HREF="http://www.xilinx.com/support/answers/45360.htm">www.xilinx.com/support/answers/45360.htm</A> for information
    on GTX General ES Settings 

  - Please refer AR 51625 - <A HREF="http://www.xilinx.com/support/answers/51625.htm">www.xilinx.com/support/answers/51625.htm</A> for information 
    on GTH General ES Settings

  - Please refer AR 53779 - <A HREF="http://www.xilinx.com/support/answers/53779.htm">www.xilinx.com/support/answers/53779.htm</A> for information
    on GTH Production Si Settings 

  - Please refer AR 51369 - <A HREF="http://www.xilinx.com/support/answers/51369.htm">www.xilinx.com/support/answers/51369.htm</A> for information
    on GTP Initial ES/General ES Settings 

  - Please refer AR 53561 - <A HREF="http://www.xilinx.com/support/answers/53561.htm">www.xilinx.com/support/answers/53561.htm</A> for information
    on GTP Production Si Settings 

  - For a comprehensive listing of Known Issues for this core, please see the IP 
    Release Notes Guide,  
    
    <A HREF="http://www.xilinx.com/support/documentation/user_guides/xtp025.pdf">www.xilinx.com/support/documentation/user_guides/xtp025.pdf</A>



6. TECHNICAL SUPPORT & FEEDBACK

   To obtain technical support, create a WebCase at <A HREF="http://www.xilinx.com/support.">www.xilinx.com/support.</A>  
   Questions are routed to a team with expertise using this product.  
   Feedback on this IP core may also be submitted under the "Leave Feedback" 
   menu item in Vivado/PlanAhead.

   Xilinx provides technical support for use of this product when used
   according to the guidelines described in the core documentation, and
   cannot guarantee timing, functionality, or support of this product for
   designs that do not follow specified guidelines.


7. CORE RELEASE HISTORY 

Date        By            Version      Description
================================================================================

04/03/2013  Xilinx, Inc.  2.5          ISE 14.5

12/18/2012  Xilinx, Inc.  2.4          ISE 14.4 and Vivado 2012.4.

10/16/2012  Xilinx, Inc.  2.3          ISE 14.3 and Vivado 2012.3.

07/25/2012  Xilinx, Inc.  2.2          ISE 14.2 and Vivado 2012.2.

04/24/2012  Xilinx, Inc.  2.1          ISE 14.1 and Vivado 2012.1; Defense Grade 
                                       7 Series and Zynq devices, Automotive 
                                       Zynq devices.

01/19/2012  Xilinx, Inc.  1.6          ISE 13.4: Minor feature enhancements, 
                                       completely backward-compatible.
08/19/2011  Xilinx, Inc.  1.5          ISE 13.3 

06/22/2011  Xilinx, Inc.  1.4          ISE 13.2: CORE Generator tool flow 
                                       Support

03/01/2011  Xilinx, Inc.  1.3          Initial release
================================================================================


8. LEGAL DISCLAIMER

  (c) Copyright 2010 - 2013 Xilinx, Inc. All rights reserved.

  This file contains confidential and proprietary information
  of Xilinx, Inc. and is protected under U.S. and
  international copyright and other intellectual property
  laws.

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  THIS COPYRIGHT NOTICE AND DISCLAIMER MUST BE RETAINED AS
  PART OF THIS FILE AT ALL TIMES.



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